Lead-Free Solders: SAC Alloys, Microstructure, and Reliability

The transition from tin-lead to lead-free solders, mandated globally by RoHS and WEEE directives since 2006, fundamentally changed the metallurgy of electronic interconnections. Sn-Ag-Cu (SAC) alloys have emerged as the dominant lead-free solder family, yet their higher melting temperatures, stiffer mechanical response, and complex ternary microstructure introduce reliability challenges — particularly under thermal cycling, drop shock, and high-temperature service — that differ substantially from the well-characterised Sn-Pb system. This article examines SAC solder metallurgy in depth: phase equilibria, solidification microstructure, intermetallic compound (IMC) formation and growth kinetics, reflow process parameters, tin whisker physics, fatigue modelling, and the alloy modifications developed to address reliability gaps.

Regulatory Background: RoHS, WEEE, and the Lead-Free Transition

The European Union’s Restriction of Hazardous Substances Directive (RoHS 1, 2002/95/EC), effective July 2006, prohibited the use of lead (and five other substances) above 0.1 wt% in homogeneous materials in electrical and electronic equipment placed on the EU market. The complementary WEEE Directive addressed end-of-life recovery. RoHS 2 (2011/65/EU), extended in scope by Delegated Directive 2015/863/EU, brought additional product categories under restriction. Japan’s JGPSSI standards and China RoHS (GB/T 26572) followed similar trajectories.

The consequence for electronics manufacturing was an industry-wide process change affecting solder paste formulation, flux chemistry, board laminate materials (requiring higher-temperature-resistant FR4 substitutes or mid-Tg laminates), component temperature ratings, and reliability qualification protocols. The IPC’s iNEMI and JEITA consortia produced the foundational reliability data (notably the NCMS/NIST lead-free roadmap and iNEMI’s backward-compatibility studies) that underpinned the transition.

Key exemptions under Annex III of RoHS 2 still permit lead in specific applications — most importantly in high-lead solders (>85 wt% Pb) used in flip-chip C4 bumps and server/telecom through-hole assemblies, and in large power semiconductor packages — because lead-free alternatives have not yet met the long-term reliability requirements of these applications. These exemptions are reviewed periodically by the European Chemicals Agency (ECHA). For context on diffusion-controlled reactions that govern IMC growth, the grain boundaries and diffusion article provides relevant background.

Sn-Ag-Cu Phase Equilibria and Solidification

The Sn-Ag-Cu Ternary System

The Sn-Ag-Cu ternary system has three binary eutectics and one ternary eutectic. The binary systems of importance are:

• Sn-Ag: eutectic at Sn-3.5Ag, 221 °C, producing β-Sn + Ag₃Sn
• Sn-Cu: eutectic at Sn-0.7Cu, 227 °C, producing β-Sn + Cu₆Sn₅
• Ag-Cu: eutectic at Ag-28Cu, 779 °C (irrelevant to solder compositions)

The ternary eutectic lies at approximately Sn-3.5Ag-0.9Cu (wt%), with a melting point of 217 °C. This is the thermodynamic lower bound for SAC alloys; commercial SAC grades are near-eutectic or slightly hypoeutectic compositions. The most widely deployed grade, SAC305 (Sn-3.0Ag-0.5Cu), melts over a narrow pasty range of approximately 217–220 °C. The liquidus surface of the Sn corner of the ternary system has been computed by CALPHAD modelling (Dinsdale et al., COST 531 database) and experimentally verified by differential scanning calorimetry (DSC) at multiple laboratories.

Solidification Sequence and Microstructure Development

For SAC305, solidification begins at the liquidus (~220 °C) with primary beta-tin dendrite nucleation. As the temperature falls through the pasty range, Ag₃Sn and Cu₆Sn₅ co-precipitate from the remaining liquid in the inter-dendritic regions until the ternary eutectic reaction is complete at 217 °C:

Ternary eutectic reaction (217 °C):
  Liquid (Sn-3.5Ag-0.9Cu) → β-Sn + Ag₃Sn + Cu₆Sn₅

Phase fractions in near-eutectic SAC305 (equilibrium estimate):
  β-Sn matrix     ~95.6 wt%
  Ag₃Sn precipitates ~3.2 wt%
  Cu₆Sn₅ rods/plates ~1.2 wt%

The morphology of the Ag₃Sn phase is critically sensitive to cooling rate. At slow cooling rates (<0.5 °C/s), Ag₃Sn forms as large, faceted plates (up to 50–100 μm length) that are brittle and act as fatigue crack initiation sites. At typical reflow cooling rates (1–3 °C/s), a mixture of fine platelets and particulate Ag₃Sn is produced. At rapid quench rates (>10 °C/s), the eutectic microstructure is extremely fine (sub-micron Ag₃Sn dispersoids), maximising fatigue resistance. This strong cooling rate dependence means that the oven profile’s post-peak cooling ramp directly governs the as-reflowed microstructure and initial reliability of the joint. See also the discussion of solidification microstructure principles in the iron-carbon phase diagram article for analogous concepts in steel.

Beta-Tin and the Tin Pest Problem

Beta-tin (β-Sn, body-centred tetragonal, stable above 13.2 °C) is the matrix phase of all SAC solders. The allotropic transformation of β-Sn to alpha-tin (α-Sn, diamond cubic) at temperatures below 13.2 °C is the basis of the historical “tin pest” phenomenon — catastrophic disintegration of pure tin components in extreme cold. In SAC solders, the presence of Ag and Cu as solutes in the β-Sn matrix significantly suppresses the β → α transformation kinetics (the transformation requires long incubation at very low temperatures), making tin pest a negligible practical concern for modern SAC assemblies above −40 °C.

A more practically significant β-Sn phenomenon in SAC joints is isothermal solidification and coarsening during thermal ageing. SAC solder joints exist close to their homologous temperature (T/Tm) even at room temperature (T/Tm ≈ 0.63 for SAC at 25 °C, compared to ≈ 0.65 for Sn-Pb). This high homologous temperature drives diffusion-mediated microstructural coarsening: Ag₃Sn particles coarsen (Ostwald ripening), β-Sn grains grow and recrystallise under cyclic strain, and Cu₆Sn₅ IMC at the interface thickens by diffusion. The result is progressive microstructural degradation during service — a fundamentally different reliability challenge from high-melting-point structural alloys.

Intermetallic Compound (IMC) Formation and Growth

Interfacial IMC During Reflow

When molten SAC solder contacts a copper pad, copper dissolves rapidly into the melt and reacts with tin to nucleate Cu₆Sn₅ at the interface. This reaction is exothermic and proceeds within seconds of initial wetting. The resulting IMC layer is characterised by scallop morphology — hemispherical Cu₆Sn₅ grains that grow into the solder bulk while maintaining contact with the copper substrate. The scallop radius increases with temperature and time as:

IMC scallop growth (parabolic approximation):
  r(t) = r₀ + A · exp(−Q/RT) · tⁿ

  where:
    r(t)  = mean scallop radius at time t (μm)
    r₀   = initial radius (~0.5 μm at first contact)
    A     = pre-exponential constant
    Q     = activation energy for Cu diffusion through Cu₆Sn₅ ≈ 47 kJ/mol
    n     = time exponent ≈ 0.33–0.5 (coarsening/growth regime)
    T     = absolute temperature (K)

Typical as-reflowed Cu₆Sn₅ layer thickness: 1–4 μm
After 1000 h / 125 °C ageing: 6–12 μm
Cu₆Sn₅ hardness: ~378 HV (vs. bulk SAC: ~15–20 HV)

Between the Cu₆Sn₅ layer and the copper substrate, a thinner Cu₃Sn (epsilon phase) layer forms preferentially during solid-state ageing rather than during liquid-state reflow. Cu₃Sn grows by diffusion of copper through the Cu₆Sn₅ layer and converts Cu₆Sn₅ to Cu₃Sn at the inner interface. Cu₃Sn is denser and harder than Cu₆Sn₅ and its formation involves a volume contraction that generates residual stress at the interface — a contributing factor to cohesive failures at or near the IMC layer after prolonged ageing.

Nickel Barrier Layer Effects

Electroless Nickel / Immersion Gold (ENIG) and ENEPIG pad finishes are widely used to prevent copper dissolution and control IMC morphology. On Ni substrates, (Cu,Ni)₆Sn₅ forms with a planar rather than scalloped morphology, suppressing the stress concentration associated with scallop tips. The Ni acts as a diffusion barrier: the activation energy for Sn diffusion through NiSn intermetallic is higher than through Cu₆Sn₅, substantially slowing interfacial IMC growth during ageing. However, ENIG surfaces are susceptible to black-pad defect — corrosive attack of the nickel layer during immersion gold deposition producing a weakened, granular Ni surface that gives poor solder adhesion. ENEPIG (with Pd interlayer) was developed specifically to prevent black-pad. For general principles of diffusion barriers in metallurgy, refer to the grain boundary segregation article.

IMC in the Solder Bulk

In addition to the interfacial IMC, Cu₆Sn₅ rods and needles can precipitate throughout the bulk solder if the copper concentration exceeds the solubility limit in β-Sn (~0.7 wt% Cu at 217 °C, dropping to ~0.01 wt% at 25 °C). This is a concern in wave soldering where repeated passes through the solder pot accumulate copper from board pads, or in applications where the solder-to-pad area ratio is very low (large IMC/solder volume ratio). Bulk Cu₆Sn₅ needles are crack initiation sites under fatigue loading. Maintaining bath copper below 0.7 wt% is a standard process control requirement for wave and selective solder pots.

SAC Alloy Family: Compositions and Selection

Silver Content Trade-off: Thermal Fatigue vs. Drop-Shock

Silver is the critical composition variable in SAC alloys. Higher Ag increases the volume fraction of Ag₃Sn precipitates, which strengthens the solder by dispersion hardening and inhibits grain boundary sliding during thermomechanical creep — improving thermal fatigue life in JEDEC JESD22-A104 (−40 to +125 °C) testing. However, higher Ag also increases joint stiffness and hardness, reducing the energy absorbed before fracture under high-strain-rate loading (drop/shock per JEDEC JESD22-B111). Consumer electronics (mobile phones, tablets) that experience repeated drop events benefit from lower-Ag SAC105 or SAC0307; automotive and industrial electronics with thermal cycling requirements favour SAC305 or SAC405.

Reflow Soldering Process Parameters

Temperature Profile Requirements

The reflow oven profile for SAC solder paste consists of four zones: preheat, soak, reflow, and cooling. The higher SAC liquidus (~217 °C vs. 183 °C for Sn-Pb) forces all subsequent profile parameters upward, with cascading implications for component temperature ratings, PCB laminate selection, and flux thermal stability.

The 20 °C increase in peak temperature is not trivial: it accelerates PCB laminate degradation (delamination risk at inner layers), increases thermal stress on ceramic capacitors (capacitor cracking), and demands that all components be rated to J-STD-020 MSL 260 °C rather than the older 240 °C rating. Components rated only for 240 °C peak cannot be used in SAC reflow processes without requalification.

Nitrogen Atmosphere Reflow

SAC alloys are more susceptible to oxidation than Sn-Pb due to the absence of lead’s surface-oxide-suppression effect. Reflow under nitrogen atmosphere (O₂ < 500 ppm, sometimes < 100 ppm for fine-pitch applications) improves wetting, reduces solder balling, minimises void formation, and permits use of lower-activity no-clean fluxes. Nitrogen consumption is a process cost that must be balanced against defect rates and rework costs; for most consumer electronics, air reflow with a well-matched no-clean flux is adequate.

Voiding in SAC Joints

Voids — gas-filled cavities within the solder joint — are a critical quality indicator. They form from: flux outgassing during reflow, entrained moisture, and solder paste vehicle decomposition. IPC-7095 specifies acceptable voiding criteria; for BGA joints, a maximum of 25% void area by cross-section is a common acceptance threshold, though tighter criteria apply for high-reliability applications. Voiding in SAC tends to be higher than in Sn-Pb due to the longer time-above-liquidus required for full wetting and the lower density differential between molten SAC and flux gas. Optimising solder paste volume, stencil aperture design, and TAL reduces voiding.

Tin Whiskers: Mechanism, Risk, and Mitigation

Tin whiskers are spontaneously grown single-crystal metallic filaments that nucleate from tin and tin-rich surfaces under compressive stress. They are among the most significant reliability risks in lead-free electronics, capable of causing intermittent or permanent electrical shorts in high-density assemblies. The risk was a key reason the electronics industry retained Sn-Pb solder through decades of regulatory pressure — Pb additions of >3 wt% are highly effective whisker suppressants.

Growth Mechanism

The driving force for whisker growth is compressive stress in the tin layer. The primary source of this stress in electroplated tin coatings on copper is the growth of Cu₆Sn₅ IMC at the Cu-Sn interface: the IMC has a larger specific volume than the Cu it replaces, generating a compressive biaxial stress in the tin overlayer. This stress is relieved by diffusive mass transport to low-energy surface sites — grain boundary grooves and surface irregularities — where whisker nucleation occurs. Once nucleated, a whisker grows by grain boundary diffusion feeding mass from the bulk to the whisker root, which pushes the whisker outward while the whisker grain remains stationary.

Key variables governing whisker growth rate and length:

• Substrate: Cu accelerates IMC-driven stress; Ni underplating substantially reduces IMC growth and whisker risk.
• Tin grain size: Bright electroplated Sn (fine columnar grains, high stress) is far more susceptible than matte Sn (equiaxed grains, lower stress). JEDEC JESD22-A121A specifies matte Sn as the minimum requirement for whisker mitigation.
• Temperature cycling: Cyclic thermal stress accelerates whisker growth above isothermal conditions by providing additional mechanical driving force.
• Alloying: Small additions of Ag (>2 wt%), Bi, Cu, or In to the Sn plating bath reduce whisker propensity by modifying grain structure and stress state.

Whisker length vs. time (empirical, isothermal):
  L(t) = L_sat · [1 − exp(−t / τ)]

  where:
    L_sat = saturation length (material and geometry dependent, 0.1–10 mm)
    τ   = time constant (weeks to months at room temperature)

Electrical short risk threshold: L > gap between adjacent conductors
  Typical PCB pad-to-pad spacing: 50–200 μm (fine-pitch ICs)
  Whisker lengths observed: up to 9 mm (documented in NASA studies)

Mitigation Strategies

JEDEC JESD201A and NASA’s tin whisker programme have established the following hierarchy of mitigation measures:

1. Nickel underplating (≥1.25 μm Ni between Cu and Sn): most effective single measure; reduces Cu diffusion and IMC-driven stress generation at source.
2. Matte Sn plating (equiaxed grain structure, Ra > 0.4 μm): lower residual stress than bright Sn; required by JEDEC JESD22-A121A for space and high-reliability applications.
3. Post-plate anneal (150 °C / 1 hour): relieves plating stress and promotes grain growth; must be performed within 24 hours of plating before IMC forms.
4. Tin-alloy plating (SnCu, SnAg, SnBi, SnIn): disrupts the pure-Sn grain structure that facilitates stress-driven diffusion.
5. Conformal coating (acrylic, polyurethane, silicone per IPC-CC-830): mechanical barrier to whisker bridging; does not prevent whisker growth but prevents shorts. Note that whiskers can penetrate some conformal coatings.
6. Tin-lead plating on component leads: still permitted for high-reliability applications under RoHS Annex III exemptions for these specific components.

Thermal Fatigue Mechanisms and Reliability Modelling

CTE Mismatch and Inelastic Strain Accumulation

Solder joint fatigue is driven by the mismatch in coefficient of thermal expansion (CTE) between the component body (typically ceramic or moulded compound, CTE ≈ 3–10 ppm/°C) and the PCB substrate (FR4, CTE ≈ 16–20 ppm/°C in-plane). During each thermal cycle, differential expansion and contraction impose a cyclic shear strain on the solder joints connecting component to board. Because SAC solder deforms by creep at service temperatures, each cycle accumulates irreversible (inelastic) strain in the joint. Fatigue crack nucleation occurs preferentially at:

• The solder-IMC interface (brittle/ductile boundary, stress concentration at IMC scallop tips)
• Large Ag₃Sn plates (crack initiation at plate edges and tips)
• Within the bulk solder at recrystallised grain boundaries (high-angle boundaries formed by cyclic deformation act as crack propagation paths)

The Coffin-Manson and Engelmaier Models

The fundamental fatigue life relationship for solder joints is the Coffin-Manson law, relating inelastic (plastic + creep) strain range to cycles to failure:

Coffin-Manson (basic form):
  N_f = C · (Δγ_in)^(-k)

  where:
    N_f      = mean cycles to failure (63.2% failure probability)
    Δγ_in = inelastic shear strain range per cycle
    C, k     = material constants (SAC305: k ≈ 1.96, C determined by test data)

Engelmaier modified model (accounts for creep and temperature):
  N_f = (1/2) · (Δγ / 2ϵ_f')^(1/c)

  c  = -0.442 - (6×10⁻⁴)·T_sj + (1.74×10⁻²)·ln(1+f)
  ϵ_f' = 0.65 (fatigue ductility coefficient, SAC, approximate)
  T_sj = mean cyclic solder joint temperature (°C)
  f    = thermal cycling frequency (cycles/day)

Shear strain range (simplified, uniform joint):
  Δγ = (L_D · Δα · ΔT) / h_s

  L_D  = distance from neutral point to critical joint (mm)
  Δα = CTE mismatch (component vs PCB) (ppm/°C)
  ΔT   = temperature range of cycle (°C)
  h_s  = solder joint height (mm)

These models form the analytical foundation of IPC-9701 (Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments). Finite element analysis (FEA) with viscoplastic constitutive models (Anand model is standard for SAC solder) is used for more accurate strain calculations in complex geometries. For background on the dislocation mechanisms that underlie creep deformation, see the grain boundary and dislocation article.

Microstructural Evolution During Fatigue

SAC solder joints do not maintain their as-reflowed microstructure during thermal cycling. Cyclic deformation progressively recrystallises the β-Sn matrix in regions of high plastic strain (typically at the corners of BGA joints and beneath ceramic chip capacitors). Recrystallised regions consist of fine, equiaxed β-Sn grains with predominantly high-angle boundaries — these boundaries provide low-resistance pathways for fatigue crack propagation. The Ag₃Sn particles simultaneously coarsen by Ostwald ripening, reducing their strengthening effectiveness. The net result is that the properties of a thermally aged SAC joint are substantially different from the as-reflowed properties — a critical consideration for accelerated testing programmes that use elevated temperature ageing as a substitute for thermal cycling.

Comparison: SAC Lead-Free vs. Sn-Pb Eutectic

Wave Soldering and Selective Soldering with Lead-Free Alloys

Reflow soldering (solder paste + oven) is the dominant process for surface mount assemblies, but wave soldering and selective soldering remain essential for through-hole components. Lead-free wave soldering presents additional challenges compared to SMT reflow:

The standard lead-free wave solder alloy is Sn-0.7Cu (Sn-Cu eutectic, 227 °C) rather than SAC, primarily because silver provides no wetting benefit in the wave process and dramatically increases alloy cost for large-volume baths. SN100C (Sn-0.7Cu-0.05Ni+Ge trace) is widely used: Ni refines Cu₆Sn₅ grain size in the pot, reducing dross formation and copper leaching from pads; Ge acts as an antioxidant at the bath surface. Wave bath temperatures of 255–265 °C are standard — 25–40 °C above Sn-Pb wave practice — requiring adjustment of conveyor speed, preheat temperature, and board support to prevent bowing and component damage.

Copper dissolution from PCB pads into the wave solder bath is a significant operational concern: at 260 °C, copper dissolves at approximately 0.3–0.5 μm per pass into Sn-0.7Cu. Bath copper content must be controlled below 1.5 wt% to prevent excessive Cu₆Sn₅ sludge formation and joint roughness. Periodic bath analysis and controlled addition of fresh alloy maintains composition within specification. The hardness testing techniques applicable to solder joint cross-sections are reviewed in the materials testing section.

Frequently Asked Questions

Recommended Reading

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Further Reading